Bulk CMOS technologies are predicted to face crucial technological challenges in the next decade. At the same time, novel devices such as Carbon Nanotube Field Effect Transistors (CNTFETs) and Silicon Nanowire Field Effect Transistors (SNWFETs), which do not suffer from the same constraints, are expected to play a primary role as devices in future ultra-large scale integration technologies.
The interest in these devices is motivated not only by their small size, but also their superior characteristics, such as quasi-ballistic transport, steep sub-threshold slopes and one-dimensional channel geometry. Channel geometry, specifically, plays a major role in the current efforts towards miniaturization of devices, with transistor manufacturers currently moving from planar bulk MOSFETs to fully depleted SOI and FinFETs. Fully depleted SOIs, in particular, exploit the presence of a buried oxide layer below the device channel to screen the drain electric field from interfering with the gate electric field, thus reducing short channel effects. Moreover, fully depleting the channel enhances the device switching speed by requiring less gate field to turn on the device. FinFETs are a further evolution of this concept, exploiting vertical fin-like device channels, which can fully deplete and can be controlled on three surfaces by the electric field. In order to obtain the best electrostatic control over the device channel, however, one-dimensional channel structures need to be implemented. These include semiconducting mono or poly-crystalline nanowires and carbon nanotubes (CNTs).
Among the types of CNTFETs demonstrated in literature, double-gate ambipolar CNTFETs are four-terminal devices where a second gate terminal is added to control the device polarity [3]. These devices combine performance exceeding that of current scaled MOSFETs, with the possibility to control the device polarity by electrostatic doping of the nano-tubes [1]. Nevertheless, CNTFETs, as well as catalyst-grown nanowires, require a bottom-up fabrication approach, where nanotubes/nanowires are first grown in dedicated furnaces and subsequently purified, selected and transferred on the final substrate. Bottom up approaches have not been successful in proposing a large-scale device integration method primarily due to the challenges in selecting and positioning channel elements on the final substrates.